STA Engineer
ACL Digital
We are looking for a skilled and motivated.The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure.Constraint creation and maintenance exposure.DFT modes in STA timing c
Last checked on May 26, 2026. We may earn a commission when you click through.
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